A configurable architecture for fast moments computation

Chang, Kah-Hyong and Paramesran, Raveendran (2015) A configurable architecture for fast moments computation. Journal of Signal Processing Systems for Signal Image and Video Technology, 78 (2). pp. 179-186. ISSN 1939-8018, DOI https://doi.org/10.1007/s11265-013-0857-9.

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Abstract

In this paper, we present a single-chip architecture for generating a full set of geometric moments using digital filters. Other types of moments such as Zernike and Tchebichef moments can also be implemented. The architecture can be configured for any order of geometric moments and image spatial resolution at run time. The use of a single-scaler method and reusable hardware resources enables higher order moments to be computed. The incorporation of two-level pipelining and masking techniques further increases the throughput. Realized in a field-programmable gate array, the design is capable of processing sixty 512 x 512 8-bit-pixel images per second at 20 MHz, generating (59 + 59) orders of geometric moments (3,600 moments). The maximum round-off error is approximately 1 .

Item Type:	Article
Funders:	UNSPECIFIED
Additional Information:	Ca6dm Times Cited:0 Cited References Count:22
Uncontrolled Keywords:	Image processing, moments, digital filters, real-time, configurable, high-order, field-programmable gatearray (fpga), zernike moments, image-analysis, recognition, invariants,
Subjects:	T Technology > T Technology (General) T Technology > TA Engineering (General). Civil engineering (General) T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions:	Faculty of Engineering
Depositing User:	Mr Jenal S
Date Deposited:	25 Jul 2015 02:22
Last Modified:	20 Sep 2019 08:32
URI:	http://eprints.um.edu.my/id/eprint/13812

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