Items where Author is "Hoo, C.S."

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Hoo, C.S. and Kanesan, J. and Ramiah, H. (2015) Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs. International Journal of Circuit Theory and Applications, 43 (3). pp. 286-306. ISSN 0098-9886, DOI https://doi.org/10.1002/cta.1939.

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