Eighteen-level inverter control with minimum switching losses

Abdul Kadir, M.N. and Mekhilef, Saad (2009) Eighteen-level inverter control with minimum switching losses. In: 2009 13th European Conference on Power Electronics and Applications, EPE '09, Barcelona.

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A multilevel multistage inverter design and its corresponding control strategy are presented. The hybrid inverter has a high voltage stage composed of the six-switch conventional three phase inverter with its outputs connected in series to the outputs of three-level H-bridge medium and low voltage stages. The voltage ratio has been selected to form 18-level provide maximum number of uniform steps. The suggested control strategy has been developed to ensure minimum switching losses focusing on holding the higher voltage stage state as long as it is feasible. The reference voltage vector has been approximated to the nearest inverter voltage vector. A special definition of state zone has been introduced for the low voltage stage to enable the achievement of the reference vector with minimum error. The proposed control strategy has been tested and its short computational time and low memory requirement has been proven.

Item Type: Conference or Workshop Item (Paper)
Additional Information: Conference code: 78515 Export Date: 16 November 2012 Source: Scopus Art. No.: 5279169 Language of Original Document: English Correspondence Address: Abdul Kadir, M. N.; Department of Electrical Engineering, Malaya University, Kuala Lumpur, Malaysia; email: makadr@yahoo.com References: Annette von Jouanne, S.D., Haoran Zhang, A., Multilevel Inverter Approach Providing DC-Link Balancing, Ride-Through Enhancement, and Common-Mode Voltage Elimination (2002) IEEE Trans. on indsut. Elect, 49 (4), pp. 739-745. , AUG; Song-Manguelle, J., Ruffer, A., Asymmetrical Multilevel inverter for large induction machine drives (2001) EDPE'01 Electrical Drives and Power Electronics International conference, Slovakia 3-5, pp. 101-107. , October; Ruffer, A., Veenstra, M., Gopakumar, K., Asymmetrical multilevel converter for high resolution voltage phasor generation EPE 99; J. Song-Manguelle, S. Mariethoz, and A. Rufer, A generalized design principle of a uniform step asymmetrical multilevel converter for high power conversion EPE-2001:Mariethoz, S., Rufer, A., (2002) Design and control of asymmetrical multi-level inverters, pp. 840-845. , IECON Industrial electronics society IEEE; Lai, Y.S., Shyu, F.S., Topology for hybrid multilevel inverter (2002) IEE Proc.-Elect. Power Appl, 149 (6). , November; Y. Liu, and F. L. Luo: Trinary hybrid 81-level multilevel inverter for motor drive with zero common-mode voltage, Industrial Electronics IEEE Transaction on, 55, Issue: 3, March 2008, pp/ 1014-21Abdul Kadir, M., Mekhilef, S., Ping, H.W., Direct torque control of permanent magnet synchronous motor drive with asymmetrical multilevel inverter supply, ICPE07, Korea October, 2007, pp. 1196-1201; Mariethoz, S., Rufer, A., An overview of the technique of asymmetrical multilevel inverters , ANAE : Associazione Nazionale Azionamenti Elettrici (2005) 16o Seminario Interattivo, Azionamenti elettrici : Evoluzione Tecnologica e Problematiche Emergenti, , Bressanone, Italy; McGrath, B.P., Holmes, D.G., Lipo, T., Optimized Space Vector Switching Sequence for Multilevel Inverters (2003) Power Electronics IEEE Transactions on, 18 (6), pp. 1293-1301. , Nov
Uncontrolled Keywords: Converter circuit, Converter control, Multilevel converters, Voltage source inverters (VSI), Computational time, Control strategies, Converter circuits, Converter controls, H-bridges, High voltage, Higher voltage stage, Hybrid inverters, Inverter control, Low memory, Low voltages, Multilevel converter, Multilevel multistage inverter, Reference vectors, Reference voltages, Switching loss, Three-level, Three-phase inverter, Voltage ratios, Voltage source inverter, Voltage vectors, Electric inverters, Photolithography, Power electronics.
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering
Depositing User: Mr Jenal S
Date Deposited: 18 Feb 2013 01:58
Last Modified: 25 Oct 2019 03:53
URI: http://eprints.um.edu.my/id/eprint/4861

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