70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing

Amouzad Mahdiraji, G. and Abdullah, M.K. and Mokhtar, M. and Mohammadi, A.M. and Abas, A.F. and Basir, S.M. and Abdullah, R.S.A.R. (2009) 70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing. Photonic Network Communications, 19 (3). pp. 233-239. ISSN 1572-8188, DOI https://doi.org/10.1007/s11107-009-0228-4.

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Abstract

The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 � 10 Gb/s, the worst receiver sensitivity of�10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±17 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity,OSNR, and chromatic dispersion tolerance are �23.5dBm, 29dB, and ±36 ps/nm, respectively.

Item Type: Article
Funders: UNSPECIFIED
Uncontrolled Keywords: Optical communications , Multiplexing , Duty cycle.
Subjects: T Technology > TA Engineering (General). Civil engineering (General)
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering
Depositing User: Mr Jenal S
Date Deposited: 18 Jun 2013 06:36
Last Modified: 18 Jun 2013 06:36
URI: http://eprints.um.edu.my/id/eprint/6221

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