Fahad, Mohammad and Siddique, Marif Daula and Iqbal, Atif and Sarwar, Adil and Mekhilef, Saad (2021) Implementation and analysis of a 15-Level inverter topology With reduced switch count. IEEE Access, 9. pp. 40623-40634. ISSN 2169-3536, DOI https://doi.org/10.1109/ACCESS.2021.3064982.
Full text not available from this repository.Abstract
Multilevel inverters remain an area of research interest due to the superior performance against a two-level counterpart. Reducing the switch count and stress on the power electronic switches while maintaining a sinusoidal stepped output remains a challenge. A multilevel inverter topology has been proposed in this work which utilizes twelve switches and four dc voltage sources to produce a 15-level staircase output voltage waveform. The objective is to reduce the harmonic in the output voltage and thereby reducing the cost of filter requirement and maintaining high efficiency throughout the operating range. Control of output voltage has been done using the Nearest Level Pulse Width Modulation Strategy (NLPWM). Simulation and hardware implementation of the topology under different loads and dynamic conditions are presented to validate the robust performance.
| Item Type: | Article |
|---|---|
| Funders: | Qatar University-Marubeni Concept to Prototype Development Research grant from the Qatar University (MCTP-CENG-2020-2) |
| Uncontrolled Keywords: | Topology; Switches; Through-silicon vias; Power harmonic filters; Multilevel inverters; Capacitors; Voltage control; Multilevel inverters; Nearest level control (NLC); Power converters; Total harmonic distortion (THD) |
| Subjects: | Q Science > QA Mathematics > QA75 Electronic computers. Computer science T Technology > TA Engineering (General). Civil engineering (General) |
| Divisions: | Faculty of Engineering > Department of Electrical Engineering |
| Depositing User: | Ms Zaharah Ramly |
| Date Deposited: | 20 Jun 2022 06:43 |
| Last Modified: | 20 Jun 2022 06:43 |
| URI: | http://eprints.um.edu.my/id/eprint/27955 |
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