A 919 MHz-923 MHz, 21 dBm CMOS power amplifier with bias modulation linearization technique achieving PAE of 29% for LoRa application

Rawat, Arvind Singh and Rajendran, Jagadheswaran and Mariappan, Selvakumar and Shasidharan, Pravinah and Aridas, Narendra Kumar and Yarman, Binboga Siddik (2022) A 919 MHz-923 MHz, 21 dBm CMOS power amplifier with bias modulation linearization technique achieving PAE of 29% for LoRa application. IEEE Access, 10. pp. 79365-79378. ISSN 2169-3536, DOI https://doi.org/10.1109/ACCESS.2022.3193689.

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This paper presents a bias modulation linearization technique for a 919 MHz -923 MHz CMOS power amplifier which employs driver voltage modulation and main amplifier split bias. Through the proposed linearization technique, it is observed that the peak third-order intercept point (OIP3) across the output power is shifting according to the bias conditions of the split-bias power amplifier (SBPA). The third-order transconductance (g(m3)) terms are suppressed at the output by phase cancellation achieved by optimization of the bias voltages of the PA. A high dynamic range bias circuit is integrated at the driver and split main to enhance the linearity of the CMOS PA, eradicating the need for pre-distortion linearizers. The two-stage SBPA is designed and fabricated in a 180 nm CMOS process with six-metal layers and a chip size of 1.820 x 1.771 mm(2) to operate at the supply voltage of 3.3 V. The bias voltages of both driver and split main stages are varied from 0 V to 2.0 V with a linear step size of 0.2 V. The proposed SBPA delivers a saturated output power (P-out) of 27 dBm with maximum power-added efficiency (PAE) of 44.4% and peak 01P3 of 39 dBm. A maximum linear P-out of 21 dBm with 29% PAE is achieved at an adjacent channel leakage ratio (ACLR) of -30 dBc and 4% error vector magnitude (EVM), satisfying the LoRa specifications.

Item Type: Article
Funders: Ministry of Education, Malaysia (Grant No: FRGS/1/2019/TK04/USM/02/14 & RUI 1001/PCEDEC/8014079)
Uncontrolled Keywords: Adjacent channel leakage ratio (ACLR); Bias circuit; Complementary metal-oxide-semiconductor (CMOS); Error vector magnitude (EVM); Intermodulation distortion (IMD); Long-range (LoRa); Power amplifier; Radio frequency power amplifier (RFPA); Third-order intercept point (OIP3)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering > Department of Electrical Engineering
Depositing User: Ms. Juhaida Abd Rahim
Date Deposited: 23 Oct 2023 07:57
Last Modified: 23 Oct 2023 07:57
URI: http://eprints.um.edu.my/id/eprint/41795

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