Extended multilevel inverter topology with reduced switch count and voltage stress

Siddique, Marif Daula and Mekhilef, Saad and Rawa, Muhyaddin and Wahyudie, Addy and Chokaev, Bekkhan and Salamov, Islam (2020) Extended multilevel inverter topology with reduced switch count and voltage stress. IEEE Access, 8. pp. 201835-201846. ISSN 2169-3536, DOI https://doi.org/10.1109/ACCESS.2020.3026616.

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For the applications related to the medium/high-power/voltage, Multilevel inverters (MLI) are widely accepted and commercially used. The performance of MLI compare to the conventional two-level inverters is significantly superior due to the insignificant amount of harmonic distortion, lower filter size, requirement of low voltage rating devices, lower electromagnetic interference, etc. However, there are a few disadvantages such as an increased number of components, a complex modulation and control strategy, and issues related to the voltage balancing of capacitors. The present paper proposes a new topology with a lower voltage rating component to improve the performance by remedying the mentioned disadvantages. Compared with existing inverter topologies, (especially higher levels), this topology requires fewer components, fewer dc sources, and gate drives. Further, voltage stress is also low. The overall costs and complexity are therefore greatly reduced, especially for higher voltage levels. The proposed topology has been compared with other similar topologies and the comparison proves the better structure of the proposed topology. To show the working of the proposed topology, a prototype has been developed and tested for a different operating condition with two different modulation techniques. All the results show the adequate performance of the inverter topology at the different real-time environment.

Item Type: Article
Funders: Deanship of Scientific Research (DSR), King Abdulaziz University, Jeddha, Saudi Arabia KEP-Msc-4-135-39, UAE-U (31R169), Asian Universities Alliance (AUA) (31R169)
Uncontrolled Keywords: Switches; Topology; Pulse width modulation; Inverters; Stress; Logic gates; Multilevel inverter; PWM technique; higher level; Reduced switch count
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering > Department of Electrical Engineering
Depositing User: Ms Zaharah Ramly
Date Deposited: 14 Apr 2023 03:16
Last Modified: 14 Apr 2023 03:16
URI: http://eprints.um.edu.my/id/eprint/37182

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