Loo, Mikki How-Wen and Ramiah, Harikrishnan and Lim, Chee Cheow (2024) A 585.9 μW complementary VCO with an LC head-and-tail filtering achieving 196.7 dBc/Hz FoM. IETE Journal of Research, 70 (2). pp. 1853-1860. ISSN 0377-2063, DOI https://doi.org/10.1080/03772063.2022.2163709.
Full text not available from this repository.Abstract
This paper reports a PMOS-NMOS Complementary LC voltage-biased oscillator with dual-second harmonic filtering tanks. It features 2 LC networks integrated each at the head and tail of the oscillator to concurrently resonate at twice the oscillating frequency (f(LO)), forming two high-impedance paths to prevent the PMOS and NMOS -g(m) differential pairs from loading the main LC resonator when the transistors are driven into the triode region. This improves the voltage and current efficiency of the oscillator. Furthermore, the gate-to-source voltages of the two -g(m) differential pairs are reshaped to reduce their phase noise contributions. Simulated in 65 nm CMOS, the proposed oscillator with 4.64-5.64 GHz (17.68%) tunability exhibits a power consumption ranging 585.9-655.4 mu W while offering a phase noise performance of -139-141.5 dBc/Hz at the 10 MHz offset. The corresponding FoM is 196.2-196.7 dBc/Hz.
| Item Type: | Article |
|---|---|
| Funders: | UNSPECIFIED |
| Uncontrolled Keywords: | CMOS; Figure-of-merit (FoM); Phase noise (PN); Second harmonic filtering; Ultra-low power (ULP); Voltage-biased oscillator; Voltage-controlled-oscillator (VCO) |
| Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
| Divisions: | Faculty of Engineering > Department of Electrical Engineering |
| Depositing User: | Ms. Juhaida Abd Rahim |
| Date Deposited: | 15 Aug 2024 07:32 |
| Last Modified: | 15 Aug 2024 07:32 |
| URI: | http://eprints.um.edu.my/id/eprint/46078 |
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