Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs

Hoo, C.S. and Kanesan, J. and Ramiah, H. (2015) Cost reduction in bottom-up hierarchical-based VLSI floorplanning designs. International Journal of Circuit Theory and Applications, 43 (3). pp. 286-306. ISSN 0098-9886, DOI

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From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time-to-market of the product. A new perturbation method, called Cull-and-Aggregate Bottom-up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable-order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two-dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference-based cost function (one-dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near-optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near-optimal outcome as compared to the other existing algorithms. Copyright (c) 2013 John Wiley & Sons, Ltd.

Item Type: Article
Funders: University of Malaya. Grant Numbers: H-16001-00-D000051, RG095/12ICT
Additional Information: Cd9fg Times Cited:0 Cited References Count:65
Uncontrolled Keywords: VLSI physical design; Layout generation; Floorplanning; Bottom-up hierarchy; Cost reduction
Subjects: T Technology > T Technology (General)
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Divisions: Faculty of Engineering
Depositing User: Mr Jenal S
Date Deposited: 04 Sep 2015 04:07
Last Modified: 04 Sep 2015 04:07

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