Rawat, Arvind Singh and Rajendran, Jagadheswaran and Mariappan, Selvakumar and Kumar, Narendra and Mak, Pui-In and Martins, Rui P. (2023) A 27-dBm, 0.92-GHz CMOS power amplifier with mode switching and a High-Q Compact Inductor (HQCI) achieving a 30 back-off PAE. IEEE Transactions on Circuits and Systems II: Express Briefs, 70 (1). pp. 121-125. ISSN 1549-7747, DOI https://doi.org/10.1109/TCSII.2022.3201670.
Full text not available from this repository.Abstract
This brief reports a 0.92-GHz two-stage power amplifier (PA) in 130-nm CMOS process with improved backoff power efficiency and linearity. The two key techniques are: a switching mechanism for adaptive device sizing of the power stage, and a high-Q compact inductor (HQCI). The PA is designed to operate in low power (LP) mode and high power (HP) mode by using an NMOS pass transistor as a switch. The PA measures a peak output power (Pout) of 27 dBm with a peak power added efficiency (PAE) of 44%. The maximum linear output power reaches 21.5 dBm thanks to our unique HQCIbased output-matching network. At the back-off output power, a 10% increment in PAE is achieved by switching the size of the power stage with the MOS switch. Maximum Pout of 21.5 dBm is measured below -30 dBc ACLR and 4% EVM for the 16-QAM/20-MHz input modulated signal. The PA has an overall chip size of 1.382 x 1.425 mm(2).
Item Type: | Article |
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Funders: | Ministry of Education, Malaysia (FRGS/1/2019/TK04/USM/02/14), Research University (Individual) (RUI 1001/PCEDEC/8014079) |
Uncontrolled Keywords: | Adaptive size; Back-off efficiency; CMOS; Intermodulation; linearity; Matching networks; Power amplifier (PA); Q-factor; Switching; Spiral inductor; Sub-GHz |
Subjects: | T Technology > TK Electrical engineering. Electronics Nuclear engineering |
Divisions: | Faculty of Engineering > Department of Electrical Engineering |
Depositing User: | Ms Zaharah Ramly |
Date Deposited: | 21 Jun 2023 12:30 |
Last Modified: | 26 Jun 2023 04:18 |
URI: | http://eprints.um.edu.my/id/eprint/39943 |
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