High-Speed shortest path co-processor design

Idris, M.Y.I.; Abu Bakar, S.; Tamil, E.M.; Razak, Z.; Noor, N.M. (2009) High-Speed shortest path co-processor design. In: 3rd Asia International Conference on Modelling and Simulation, MAY 25-29, 2009, Bundang, INDONESIA .

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Abstract

Shortest path algorithms are significant in graph theory and have been applied in many applications such as transportation and networking. Most of the shortest path calculation is performed on general purpose processor where instructions must be run to read the input, compute the result, and set the output which later on will slow down the overall performance. Therefore, the authors proposed a hardware approach which implements FPGA technology to find the shortest path between two nodes. The FPGA approach will demonstrate how parallelism can be used to significantly reduce calculation steps compared to sequential effort. In this paper, A-Star algorithm has been chosen for the shortest path calculation since it can achieve superior time running based on its heuristic behavior.

Item Type: Conference or Workshop Item (Paper)
Creators:
  1. Idris, M.Y.I.(University of Malaya)
  2. Abu Bakar, S.(University of Malaya)
  3. Tamil, E.M.(University of Malaya)
  4. Razak, Z.(University of Malaya)
  5. Noor, N.M.(University of Malaya)
Additional Information: Univ Malaya, Dept Syst & Comp Technol, Fac Comp Sci & Informat Technol, Kuala Lumpur, Malaysia
Uncontrolled Keywords: Shortest Path; A-Star Algorithm; FPGA Implementation
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions: Faculty of Computer Science & Information Technology
Depositing User: Mr. Faizal Hamzah
Date Deposited: 23 Nov 2011 09:42
Last Modified: 23 Nov 2011 09:42
URI: http://eprints.um.edu.my/id/eprint/2287

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